(robot_ai_env) amd@ALOK-amd-HP-ZBook-Ultra-G1a:~/Downloads/MIGRAPHx$ python matrix_calculator.py --architecture rdna3 --list-instructions
Available instructions in the RDNA3 architecture:
    v_wmma_f32_16x16x16_f16
    v_wmma_f32_16x16x16_bf16
    v_wmma_f16_16x16x16_f16
    v_wmma_bf16_16x16x16_bf16
    v_wmma_i32_16x16x16_iu8
    v_wmma_i32_16x16x16_iu4
(robot_ai_env) amd@ALOK-amd-HP-ZBook-Ultra-G1a:~/Downloads/MIGRAPHx$ python matrix_calculator.py --architecture rdna3 --detail-instruction --instruction v_wmma_f16_16x16x16_f16
Architecture: RDNA3
Instruction: V_WMMA_F16_16X16X16_F16
    Encoding: VOP3P
    VOP3P Opcode: 0x42
    Matrix Dimensions:
        M: 16
        N: 16
        K: 16
    Execution statistics:
        FLOPs: 8192
        Execution cycles: 32
        FLOPs/WGP/cycle: 1024
        Can co-execute with VALU: False
    Wave32 register usage:
        GPRs required for A: 8
        GPRs required for B: 8
        GPRs required for C: 8
        GPRs required for D: 8
        GPR alignment requirement: 4 bytes
    Wave64 register usage:
        GPRs required for A: 8
        GPRs required for B: 8
        GPRs required for C: 4
        GPRs required for D: 4
        GPR alignment requirement: 4 bytes
    VOP3P register encoding:
        A matrix source field: Src0
        B matrix source field: Src1
        C matrix source field: Src2
        D matrix source field: Vdst
    Register data types:
        Src0: FP16 (IEEE binary16 floating point)
        Src1: FP16 (IEEE binary16 floating point)
        Src2: FP16 (IEEE binary16 floating point)
        Vdst: FP16 (IEEE binary16 floating point)
    Register modifiers:
        OPSEL[1:0] supported: False
        OPSEL[2] supported: True
        NEG bits supported: True
    Wave32 matrix element to register mapping with no modifiers:
        A[i][k] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        A[i][k] Lane: i and i+16
        B[k][j] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        B[k][j] Lane: j and j+16
        C or D[i][j] GPR: (floor(i / 2)).[15:0]
        C or D[i][j] Lane: ((16 * i) % 32) + j
    Wave64 matrix element to register mapping with no modifiers:
        A[i][k] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        A[i][k] Lane: i, i+16, i+32, and i+48
        B[k][j] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        B[k][j] Lane: j, j+16, j+32, and j+48
        C or D[i][j] GPR: (floor(i / 4)).[15:0]
        C or D[i][j] Lane: ((16 * i) % 64) + j
    Wave32 register to matrix element mapping with no modifiers:
        A i: (lane % 16)
        A k: 2 * GPR_num + floor(GPR_bits / 16)
        B j: (lane % 16)
        B k: 2 * GPR_num + floor(GPR_bits / 16)
        C or D i: (2 * GPR_num + floor(lane / 16)).[15:0]
        C or D j: (lane % 16)
    Wave64 register to matrix element mapping with no modifiers:
        A i: (lane % 16)
        A k: 2 * GPR_num + floor(GPR_bits / 16)
        B j: (lane % 16)
        B k: 2 * GPR_num + floor(GPR_bits / 16)
        C or D i: (4 * GPR_num + floor(lane / 16)).[15:0]
        C or D j: (lane % 16)
(robot_ai_env) amd@ALOK-amd-HP-ZBook-Ultra-G1a:~/Downloads/MIGRAPHx$ python matrix_calculator.py --architecture rdna3 --detail-instruction --instruction v_wmma_bf16_16x16x16_bf16
Architecture: RDNA3
Instruction: V_WMMA_BF16_16X16X16_BF16
    Encoding: VOP3P
    VOP3P Opcode: 0x43
    Matrix Dimensions:
        M: 16
        N: 16
        K: 16
    Execution statistics:
        FLOPs: 8192
        Execution cycles: 32
        FLOPs/WGP/cycle: 1024
        Can co-execute with VALU: False
    Wave32 register usage:
        GPRs required for A: 8
        GPRs required for B: 8
        GPRs required for C: 8
        GPRs required for D: 8
        GPR alignment requirement: 4 bytes
    Wave64 register usage:
        GPRs required for A: 8
        GPRs required for B: 8
        GPRs required for C: 4
        GPRs required for D: 4
        GPR alignment requirement: 4 bytes
    VOP3P register encoding:
        A matrix source field: Src0
        B matrix source field: Src1
        C matrix source field: Src2
        D matrix source field: Vdst
    Register data types:
        Src0: BF16 (Brain floating point)
        Src1: BF16 (Brain floating point)
        Src2: BF16 (Brain floating point)
        Vdst: BF16 (Brain floating point)
    Register modifiers:
        OPSEL[1:0] supported: False
        OPSEL[2] supported: True
        NEG bits supported: True
    Wave32 matrix element to register mapping with no modifiers:
        A[i][k] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        A[i][k] Lane: i and i+16
        B[k][j] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        B[k][j] Lane: j and j+16
        C or D[i][j] GPR: (floor(i / 2)).[15:0]
        C or D[i][j] Lane: ((16 * i) % 32) + j
    Wave64 matrix element to register mapping with no modifiers:
        A[i][k] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        A[i][k] Lane: i, i+16, i+32, and i+48
        B[k][j] GPR: floor(k / 2).[16*(k % 2)+15 : 16*(k % 2)]
        B[k][j] Lane: j, j+16, j+32, and j+48
        C or D[i][j] GPR: (floor(i / 4)).[15:0]
        C or D[i][j] Lane: ((16 * i) % 64) + j
    Wave32 register to matrix element mapping with no modifiers:
        A i: (lane % 16)
        A k: 2 * GPR_num + floor(GPR_bits / 16)
        B j: (lane % 16)
        B k: 2 * GPR_num + floor(GPR_bits / 16)
        C or D i: (2 * GPR_num + floor(lane / 16)).[15:0]
        C or D j: (lane % 16)
    Wave64 register to matrix element mapping with no modifiers:
        A i: (lane % 16)
        A k: 2 * GPR_num + floor(GPR_bits / 16)
        B j: (lane % 16)
        B k: 2 * GPR_num + floor(GPR_bits / 16)
        C or D i: (4 * GPR_num + floor(lane / 16)).[15:0]
        C or D j: (lane % 16)
(robot_ai_env) amd@ALOK-amd-HP-ZBook-Ultra-G1a:~/Downloads/MIGRAPHx$